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? semiconductor components industries, llc, 2011 february, 2011 ? rev. 11 1 publication order number: ncp1230/d ncp1230 low-standby power high performance pwm controller the ncp1230 represents a major leap towards achieving low standby power in medium ? to ? high power switched ? mode power supplies such as notebook adapters, off ? line battery chargers and consumer electronics equipment. housed in a compact 8 ? pin package (soic ? 8, soic ? 7, or pdip ? 7), the ncp1230 contains all needed control functionality to build a rugged and efficient power supply. the ncp1230 is a current mode controller with internal ramp compensation. among the unique features offered by the ncp1230 is an event management scheme that can disable the front ? end pfc circuit during standby, thus reducing the no load power consumption. the ncp1230 itself goes into cycle skipping at light loads while limiting peak current (to 25% of nominal peak) so that no acoustic noise is generated. the ncp1230 has a high ? voltage startup circuit that eliminates external components and reduces power consumption. the ncp1230 also features an internal latching function that can be used for ovp protection. this latch is triggered by pulling the cs pin above 3.0 v and can only be reset by pulling v cc to ground. true overload protection, internal 2.5 ms soft ? start, internal leading edge blanking, internal frequency dithering for low emi are some of the other important features offered by the ncp1230. features ? current ? mode operation with internal ramp compensation ? internal high ? voltage startup current source for loss ? less startup ? extremely low no ? load standby power ? skip ? cycle capability at low peak currents ? direct connection to pfc controller for improved no ? load standby power ? internal 2.5 ms soft ? start ? internal leading edge blanking ? latched primary overcurrent and overvoltage protection ? short ? circuit protection independent of auxiliary level ? internal frequency jittering for improved emi signature ? +500 ma/ ? 800 ma peak current drive capability ? available in three frequency options: 65 khz, 100 khz, and 133 khz ? direct optocoupler connection ? spice models available for transient and ac analysis ? this is a pb ? free device typical applications ? high power ac ? dc adapters for notebooks, etc. ? offline battery chargers ? set ? top boxes power supplies, tv, monitors, etc. marking diagram xxx = device code: 65, 100, 133 y = device code: 6, 1, 1 y = device code: 5 , 0 , 3 a = assembly location l = wafer lot y, yy = year w, ww = work week g = pb ? free package = pb ? free package (note: microdot may be in either location) http://onsemi.com pdip ? 7 vhvic p suffix case 626b 1 8 1 8 soic ? 8 vhvic d suffix case 751 pin connections drv gnd 18 v cc cs fb hv pfc vcc see detailed ordering and shipping information in the ordering information section on page 4 of this data sheet. ordering information 1230pxxx awl yywwg 1 1 8 soic ? 7 d1 suffix case 751u 30d16 alyw 1 8 230dy alywy 1 8
ncp1230 http://onsemi.com 2 figure 1. typical application example 1 8 2 3 4 7 6 5 cbulk hv + mc33262/33260 pfc_v cc ovp 1 8 2 3 4 7 6 5 ncp1230 ovp + gn d v out rsense gnd ramp comp 10 k v cc cap pin function description pin no. pin name function pin description 1 pfc v cc this pin provides the bias voltage to the pfc controller. this pin is a direct connection to the v cc pin (pin 6) via a low impedance switch. in standby and during the startup sequence, the switch is open and the pfc v cc is shut down. as soon as the aux. winding is stabilized, pin 1 connects to the v cc pin and provides bias to the pfc controller. it goes down in standby and fault conditions. 2 fb feedback signal an optocoupler collector pulls this pin low to regulate. when the current setpoint reaches 25% of the maximum peak, the controller skips cycles. 3 cs/ovp current sense this pin incorporates three different functions: the current sense function, an internal ramp compensation signal and a 3.0 v latch ? off level which latches the output off until v cc is recycled. 4 gnd ic ground ? 5 drv driver output with a drive capability of +500 ma / ? 800 ma, the ncp1230 can drive large qg mosfets. 6 v cc v cc input the controller accepts voltages up to 18 v and features a uvlo turn ? off threshold of 7.7 v typical. 7 nc ? ? 8 hv high ? voltage this pin connects to the bulk voltage and offers a lossless startup sequence. the charging current is high enough to support the bias needs of a pwm controller through pin 1.
ncp1230 http://onsemi.com 3 figure 2. internal circuit architecture + + + + + + 1 2 3 gnd cs fb pfc_vcc pfc_vcc 125 msec timer vdd_fb pfc_vcc skip vdd error leb soft ? start ramp (1v max) 10 v 10 v 20k 55k 25k 18k 1.25 vdc 0.75 vdc 3.0 vdc 2.5 msec ss timer pwm latch ? off thermal shutdown vccreset osc 2.3 vpp ramp frequency modulation / 2 4.0 vdc 4vcomp 3.2 madc 20v drv vcc hv 8 6 5 internal bias vcc mgmt vccoff=12.6v vccmin=7.7v vcclatch=5.6v q r s q r s 4 sw1 ? ? ? ? ? ? fault
ncp1230 http://onsemi.com 4 maximum ratings (notes 1 and 2) rating symbol value unit maximum voltage on pin 8 maximum current v ds i c2 ? 0.3 to 500 100 v ma power supply voltage, pin 6 current v cc i cc2 ? 0.3 to 18 100 v ma drive output voltage, pin 5 drive current v dv i o 18 1.0 v a voltage current sense pin, pin 3 current v cs i cs 10 100 v ma voltage feedback, pin 2 current v fb i fb 10 100 v ma voltage, pin 1 maximum continuous current flowing from pin 1 v pfc i pfc 18 35 v ma thermal resistance, junction ? to ? air, pdip version r ja 100 c/w thermal resistance, junction ? to ? air, soic version r ja 178 c/w maximum power dissipation @ t a = 25 c pdip soic p max 1.25 0.702 w maximum junction temperature t j 150 c storage temperature range t stg ? 60 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: pin 1 ? 6: human body model 2000 v per mil ? std ? 883, method 3015. machine model method 200 v pin 8 is the hv startup of the device and is rated to the maximum rating of the part, or 500 v. 2. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78. ordering information device package shipping ? ncp1230d165r2g soic ? 7 (pb ? free) 2500 / tape & reel ncp1230d65r2g soic ? 8 (pb ? free) 2500 / tape & reel ncp1230d100r2g soic ? 8 (pb ? free) 2500 / tape & reel ncp1230d133r2g soic ? 8 (pb ? free) 2500 / tape & reel ncp1230p65g pdip ? 7 (pb ? free) 50 units/ rail ncp1230p100g pdip ? 7 (pb ? free) 50 units/ rail ncp1230p133g pdip ? 7 (pb ? free) 50 units/ rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1230 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 13 v, v pin8 = 30 v unless otherwise noted.) characteristic symbol pin min typ max unit supply section (all frequency versions, otherwise noted) turn ? on threshold level, v cc going up (v fb = 2.0 v) v ccoff 6 11.6 12.6 13.6 v minimum operating voltage after turn ? on v cc(min) 6 7.0 7.7 8.4 v v cc decreasing level at which the latch ? off phase ends (v fb = 3.5 v) v cclatch 6 5.0 5.6 6.2 v v cc level at which the internal logic gets reset v ccreset 6 ? 4.0 ? v internal ic consumption, no output load on pin 6 (v fb = 2.5 v) i cc1 6 0.6 1.1 1.8 ma internal ic consumption, 1.0 nf output load on pin 6, f sw = 65 khz (v fb = 2.5 v) i cc2 6 1.3 1.8 2.5 ma internal ic consumption, 1.0 nf output load on pin 6, f sw = 100 khz i cc2 6 1.3 2.2 3.0 ma internal ic consumption, 1.0 nf output load on pin 6, f sw = 133 khz i cc2 6 1.3 2.8 3.3 ma internal ic consumption, latch ? off phase i cc3 6 400 680 1000 a internal startup current source high ? voltage current source, 1.0 nf load (v ccoff ? 0.2 v, v fb = 2.5 v, v pin8 = 30 v) i c1 8 1.8 3.2 4.2 ma high ? voltage current source (v cc = 0 v) i c2 8 1.8 4.4 5.6 ma minimum startup voltage (i c = 0.5 ma, v ccoff ? 0.2 v, v fb = 2.5 v) v hvmin 8 ? 20 23 v startup leakage (v pin8 = 500 v) i hvleak 8 10 30 80 a drive output output voltage rise ? time @ c l = 1.0 nf, 10 ? 90% of output signal t r 5 ? 40 ? ns output voltage fall ? time @ c l = 1.0 nf, 10 ? 90% of output signal t f 5 ? 15 ? ns source resistance, r load 300 (v fb = 2.5 v) r oh 5 6.0 12.3 25 sink resistance, at 1.0 v on pin 5 (v fb = 3.5 v) r ol 5 3.0 7.5 18 pin 1 output impedance (or r dson between pin 1 and pin 6 when sw1 is closed) r load on pin 1 = 680 rpfc 1 6.0 11.7 23 current comparator and thermal shutdown input bias current @ 1.0 v input level on pin 3 i ib 3 ? 0.02 ? a maximum internal current setpoint tj = 25 c tj = ? 40 c to +125 c i limit 3 1.010 0.979 1.063 ? 1.116 1.127 v default internal setpoint for skip cycle operation and standby detection v skip 3 600 750 900 mv default internal setpoint to leave standby v stby ? out ? 1.0 1.25 1.5 v propagation delay from cs detected to gate turned off (v gate = 10 v) (pin 5 loaded by 1.0 nf) t del cs 3 ? 90 180 ns leading edge blanking duration t leb 3 100 200 350 ns soft ? start period (note 3) ss ? ? 2.5 ? ms temperature shutdown, maximum value (note 3) t sd ? 150 165 ? c hysteresis while in temperature shutdown (note 3) t sd hyste ? ? 25 ? c 3. verified by design.
ncp1230 http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 13 v, v pin8 = 30 v unless otherwise noted.) characteristic symbol pin min typ max unit internal oscillator oscillation frequency, 65 khz version (v fb = 2.5 v) tj = 25 c tj = 0 c to +125 c tj = ? 40 c to +125 c f osc ? 60 58 55 65 ? ? 70 72 72 khz oscillation frequency, 100 khz version tj = 25 c tj = 0 c to +125 c tj = ? 40 c to +125 c f osc ? 93 90 85 100 ? ? 107 110 110 khz oscillation frequency, 133 khz version tj = 25 c tj = 0 c to +125 c tj = ? 40 c to +125 c f osc ? 123 120 113 133 ? ? 143 146 146 khz internal modulation swing, in percentage of f sw (v fb = 2.5 v) (note 4) ? ? ? 6.4 ? % internal swing period (note 4) ? ? ? 5.0 ? ms maximum duty ? cycle (cs = 0, v fb = 2.5 v) d max ? 75 80 85 % internal ramp compensation internal resistor (note 4) r up 3 9.0 18 36 k ramp compensation sawtooth amplitude ? 3 ? 2.3 ? vpp feedback section opto current source (v fb = 0.75 v) ? 2 200 235 270 a pin 3 to current setpoint division ratio (note 4) i ratio ? ? 2.8 ? ? protection timeout before validating short ? circuit or pfc v cc (note 4) t del ? ? 125 ? ms latch ? off level v latch 3 2.7 3.0 3.3 v 4. verified by design. figure 3. v cc ( off ) threshold vs. temperature typical performance characteristics figure 4. v cc ( min ) threshold vs. temperature 7.0 7.2 7.4 7.6 7.8 8.0 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 150 v pin8 = 30 v v cc(min) threshold (v) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 12.0 12.2 12.4 12.6 12.8 13.0 v cc(off) , threshold (v) 150 v cc = 0 v v pin8 = 30 v
ncp1230 http://onsemi.com 7 typical performance characteristics figure 5. v cc latch threshold vs. temperature figure 6. i cc1 internal current consumption, no load vs. temperature figure 7. i cc2 internal current consumption, 1.0 nf load vs. temperature figure 8. i cc3 internal consumption, latch ? off phase vs. temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 5.0 5.2 5.4 5.6 5.8 6.0 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.6 0.85 1.1 1.35 1.6 t j , junction temperature ( c) 1.5 1.9 2.3 2.7 3.1 125 100 75 50 25 0 ? 25 ? 50 400 500 700 600 800 v cc latch threshold (v) 150 v pin8 = 30 v 150 i cc1 (ma) v cc = 13 v t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 150 v cc = 13 v i cc2 (ma) 150 i cc3 ( a) 133 khz 100 khz 65 khz t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 2.0 2.5 3.0 3.5 4.0 125 100 75 50 25 0 ? 25 ? 50 3.0 3.5 4.0 4.5 5.0 i c1 (ma) 150 v cc = v cc ? 0.2 v v pin8 = 30 v i c2 (ma) 15 0 v pin8 = 30 v v cc = 0 v figure 9. i c1 startup current vs. temperature figure 10. i c2 startup current vs. temperature
ncp1230 http://onsemi.com 8 t j , junction temperature ( c) 19.0 20.0 20.5 21.0 21.5 22.0 125 100 75 50 25 0 ? 25 ? 50 8.0 10 12 16 18 5.0 8.0 10 11 15 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 150 v cc = v cc(off) ? 0.2 v v hv minimum (v) 150 drive source resistance ( ) v cc = 13 v t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 150 v cc = 13 v drive sink resistance ( ) 14 6.0 7.0 9.0 13 14 12 typical performance characteristics figure 11. minimum startup voltage vs. temperature figure 12. leakage current vs. temperature figure 13. drive source resistance vs. temperature figure 14. drive sink resistance vs. temperature 19.5 0 50 75 100 v drain , voltage (v) 850 800 600 400 200 50 10 1 950 v cc = 13 v leakage current ( a) 25 t j = ? 40 c t j = +25 c t j = +125 c t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 1.00 1.10 1.20 i limit (v) 15 0 v cc = 13 v 0.90 0.95 1.05 1.15 figure 15. rpfc vs. temperature figure 16. i limit vs. temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 8.0 9.0 12 14 16 18 150 v cc = 13 v rpfc, resistance ( ) 10 11 13 15 17 min typ max
ncp1230 http://onsemi.com 9 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 700 725 750 775 800 t j , junction temperature ( c) 1.10 1.15 1.20 1.30 1.35 1.40 125 100 75 50 25 0 ? 25 ? 50 1.5 2.0 2.5 3.5 4.0 v skip (mv) 150 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 15 0 v stby ? out (v) 150 soft ? start (ms) v cc = 13 v 3.0 v cc = 13 v 1.25 typical performance characteristics figure 17. v skip vs. temperature figure 18. v stby ? out vs. temperature figure 19. soft ? start vs. temperature figure 20. frequency (65 khz) vs. temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 50 60 70 80 150 frequency (khz) v cc = 13 v 55 65 75 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 90 94 98 106 110 150 frequency (khz) v cc = 13 v 102 figure 21. frequency (100 khz) vs. temperature figure 22. frequency (133 khz) vs. temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 125 129 133 141 145 15 0 frequency (khz) v cc = 13 v 137
ncp1230 http://onsemi.com 10 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 79.0 80.0 81.0 150 v cc = 13 v duty cycle max (%) 79.5 typical performance characteristics t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 10 18 20 150 12 16 14 r up (k ) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 230 260 280 i opto ( a) 150 200 210 240 270 220 250 v fb = 0.75 v 80.5 4.0 6.0 10.0 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 150 v cc = 13 v internal modulation swing (%) 5.0 7.0 f osc = 65 khz 8.0 9.0 figure 23. internal modulation swing vs. temperature figure 24. maximum duty cycle vs. temperature figure 25. i opto vs. temperature figure 26. internal ramp compensation resistor vs. temperature v cc = 13 v 22 24 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 2.50 3.00 3.50 vl atch (v) 150 2.75 3.25 figure 27. fault time delay vs. temperature figure 28. vl atch vs. temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 100 140 150 150 110 130 120 t del fault time delay (ms)
ncp1230 http://onsemi.com 11 operating description introduction the ncp1230 is a current mode controller which provides a high level of integration by providing all the required control logic, protection, and a pwm drive output into a single chip which is ideal for low cost, medium to high power off ? line application, such as notebook adapters, battery chargers, set ? boxes, tv, and computer monitors. the ncp1230 can be connected directly to a high voltage source providing lossless startup, and eliminating external startup circuitry. in addition, the ncp1230 has a pfc_v cc output pin which provides the bias supply power for a power factor correction controller, or other logic. the ncp1230 has an event management scheme which disables the pfc_v cc output during standby, and overload conditions. pfc_v cc as shown on the internal ncp1230 diagram, an internal low impedance switch sw1 routes pin 6 (v cc ) to pin 1 when the power supply is operating under nominal load conditions. the pfc_v cc signal is capable of delivering up to 35 ma of continuous current for a pfc controller, or other logic. connecting the ncp1230 pfc_v cc output to a pfc controller chip is very straight forward, refer to the ?t ypical application example? all that is generally required is a small decoupling capacitor (0.1 f). figure 29. typical application example 1 8 2 3 4 7 6 5 high voltage mc33262/33260 1 8 2 3 4 7 6 5 ncp1230 + gnd v out rsense gnd v cc cap pfc_v cc
ncp1230 http://onsemi.com 12 feedback the feedback pin has been designed to be connected directly to the open ? collector output of an optocoupler. the pin is pulled ? up through a 20 k resistor to the internal vdd_fb supply (5 volts nominal). the feedback input signal is divided down, by a factor of three, and connected to the negative ( ? ) input of the pwm comparator. the positive (+) input to the pwm comparator is the current sense signal (figure 30). the ncp1230 is a peak current mode controller, where the feedback signal is proportional to the output power. at the beginning of the cycle, the power switch is turns ? on and the current begins to increase in the primary of the transformer, when the peak current crosses the feedback voltage level, the pwm comparators switches from a logic level low, to a logic level high, resetting the pwm latching flip ? flop, turning off the power switch until the next oscillator clock cycle begins. figure 30. vdd_fb + ? fb pwm 2.3 vpp ramp leb 20k 18k 25k 55k 10 v 2 3 the feedback pin input is clamped to a nominal 10 volt for esd protection. skip mode the feedback input is connected in parallel with the skip cycle logic (figure 31). when the feedback voltage drops below 25% of the maximum peak current (1.0 v/rsense) the ic prevents the current from decreasing any further and starts to blank the output pulses. this is called the skip cycle mode. while the controller is in the burst mode the power transfer now depends upon the duty cycle of the pulse burst width which reduces the average input power demand. v c i pk r s 3 where: v c = control voltage (feedback pin input), i pk = peak primary current, r s = current sense resistor, 3 = feedback divider ratio. skiplevel 3v 25% 0.75v i pk 0.75 r s 3 where: i pk r s 1v i pk 2 p in l p f where: p in = is the power level where the ncp1230 will go into the skip mode l p = primary inductance f = ncp1230 controller frequency p in l p f i pk 2 2 p in p out eff where: eff = the power supply efficiency r out e out 2 p out figure 31. + 125 ms ? + ? + fb + vskip s r pfc_v cc cs cmp latch reset vskip / vstby ? out s is rising edge triggered r is falling edge triggered vdd_fb 1.25 v 0.75 v during the skip mode the pfc_vcc signal (pin 1) is asserted into a high impedance state when a light load condition is detected and confirmed, figure 32 shows typical waveforms. the first section of the waveform shows a normal startup condition, where the output voltage is low, as a result the feedback signal will be high asking the controller to provide the maximum power to the output. the second phase is under normal loading, and the output is in regulation. the third phase is when the output power drops below the 25% threshold (the feedback voltage drops to 0.75 volts). when this occurs, the 125 msec timer starts, and if the conditions is still present after the time output period, the
ncp1230 http://onsemi.com 13 ncp1230 confirms that the low output power condition is present, and the internal sw1 opens, and the pfc_vcc signal output is shuts down. while the ncp1230 is in the skip mode the fb pin will move around the 750 mv threshold level, with approximately 100 mvp ? p of hysteresis on the skip comparator, at a period which depends upon the (light) loading of the power supply and its various time constants. since this ripple amplitude superimposed over the fb pin is lower than the second threshold (1.25 volt), the pfc_vcc comparator output stays high (pfc_vcc output pin 1 is low). in phase four , the output power demands have increases and the feedback voltage rises above the 1.25 volts threshold, the ncp12 30 exits the skip mode, and returns to normal operation. figure 32. regulation 1.25 v 0.75 v skip + 60% pfc is off pfc is on pfc is on no delay 125 ms delay max i p pfc is off v fb leaving standby (skip mode) when the feedback voltage rises above the 1.25 volts reference (leaving standby) the skip cycle activity stops and sw1 immediately closes and restarts the pfc, there is no delay in turning on sw1 under these conditions, refer to figure 32. current sense the ncp1230 is a peak current mode controller, where the current sense input is internally clamped to 1.0 v, so the sense resister is determined by rsense = 1.0 v /ipk maximum. there is a 18k resistor connected to the cs pin, the other end of the 18k resistor is connect to the output of the internal oscillator for ramp compensation (refer to figure 33). ramp compensation in switch mode power supplies operating in continuous conduction mode (ccm) with a duty ? cycle greater than 50%, oscillation will take place at half the switching frequency. to eliminate this condition, ramp compensation can be added to the current sense signal to cure sub harmonic oscillations. to lower the current loop gain one typically injects between 50 and 100% of the inductor down slope. the ncp1230 provides an internal 2.3 vpp ramp which is summed internally through a 18 k resistor to the current sense pin. to implement ramp compensation a resistor needs to be connected from the current sense resistor, to the current sense pin 3. example: if we assume we are using the 65 khz version of the ncp1230, at 65 khz the dv/dt of the ramp is 130 mv/ s. assuming we are designing a flyback converter which has a primary inductance, lp, of 350 h, and the smps has a +12 v output with a np:ns ratio of 1:0.1. the off time primary current slope is given by: (v out v f) ns np l p = 371 ma/ s or 37 mv/ s when imposed on a current sense resistor (rsense) of 0.1 . if we select 75% of the inductor current downslope as our required amount of ramp compensation, then we shall inject 27 mv/ s. with our internal compensation being of 130 mv, the divider ratio ( divratio ) between rcomp and the 18 k is 0.207. therefore: r comp 18k divratio (1 divratio) = 4.69 k figure 33. + ? cs leb 18 k rcomp rsense fb/3 2.3 v 0v
ncp1230 http://onsemi.com 14 leading edge blanking in switch mode power supplies (smps) there can be a large current spike at the beginning of the current ramp due to the power switch gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. to prevent prematurely turning off the pwm drive output, a leading edges blanking (leb) (figure 34) circuit is place is series with the current sense input, and pwm comparator. the leb circuit masks the first 250 ns of the current sense signal. figure 34. - + + - cs vccreset latch ? off r s q fb/3 2.3 vpp ramp thermal shutdown skip 125 msec timer pwm comparator 18 k 10 v leb 3 v 3 250 ns short ? circuit condition the ncp1230 is different from other controllers which use an auxiliary windings to detect events on the isolated secondary output. there maybe some conditions (for example when the leakage inductance is high) where it can be extremely difficult to implement short ? circuit and overload protection. this occurs because when the power switch opens, the leakage inductance superimposes a large spike on the switch drain voltage. this spike is seen on the isolated secondary output and on the auxiliary winding. because the auxiliary winding and diode form a peak rectifier, the auxiliary vcc capacitor voltage can be charged up to the peak value rather than the true plateau which is proportional to the output level. to resolve these issues the ncp1230 monitors the 1.0 v error flag. as soon as the internal 1.0 v error flag is asserted high, a 125 ms timer starts. if at the end of the 125 ms timeout period, the error flag is still asserted then the controller determines that there is a true fault condition and stops the pwm drive output, refer to figure 35. when this occurs, vcc starts to decrease because the power supply is locked out. when vcc drops below uvlolow (7.7 v typical), it enters a latch ? off phase where the internal consumption is reduced down to 680 a (typical). the voltage on the vcc capacitor continues to drop, but at a lower rate. when vcc reaches the latch ? off level (5.6 v), the current source is turned on and pulls vcc above uvlohigh. to limit the fault output power, a divide ? by ? two circuit is connected to the vcc pin that requires two startup sequences before attempting to restart the power supply. if the fault has gone and the error flag is low, the controller resumes normal operations. under transient load conditions, if the error flag is asserted, the error flag will normally drop prior to the 125 ms timeout period and the controller continues to operate normally. if the 125 msec timer expires while the ncp1230 is in the skip mode, sw1 opens and the pfc_vcc output will shut down and will not be activated until the fault goes away and the power supply resumes normal operations. while in the skip mode, to avoid any thermal runaway it is desirable for the burst duty cycle to be kept below 20%(the burst duty ? cycle is defined as tpulse / tfault).
ncp1230 http://onsemi.com 15 figure 35. 125ms 12.6v 7.7v 125ms 125ms 125ms the latch ? off phase can also be initiated, more classically, when vcc drops below uvlo (7.7 v typical). during this fault detection method, the controller will not wait for the 125 ms time ? out, or the error flag before it goes into the latch ? off phase, operating in the skip mode under these conditions, refer to figure 36. figure 36. regulation 125 ms fault regulation pfc v cc 1 v flag timer 5.6 v 7.7 v 12.6 v v cc pwm 125 ms 2.5 ms ss
ncp1230 http://onsemi.com 16 current sense input pin latch ? off the ncp1230 features a fast comparator (figure 34) that monitors the current sense pin during the controller off time. if for any reason the voltage on pin 3 increases above 3.0 v, the ncp1230 immediately stops the pwm drive pulses and permanently stays latched off until the bias supply to the ncp1230 is cycled down (vcc must drop below 4.0 v, e.g. when the user unplugs the converter from the mains). this offers the designer the flexibility to implement an externally shutdown circuit (for example for overvoltage or overtemperature conditions). when the controller is latched off through pin 3 (current sense), sw1 opens and shuts off pfc_vcc output. figure 37 shows how to implement the external latch via a zener diode and a simple pnp transistor. the pnp actually samples the zener voltage during the off time only, hence leaving the cs information un ? altered during the on time. various component arrangements can be made, e.g. adding a ntc device for the over temperature protection (otp). figure 37. connecting the pnp to the drive only activates the offset generation during toff. here is a solution monitoring the auziliary vcc rail. 1 2 3 4 5 8 6 7 ramp 1k cvcc hv vz drive output the ncp1230 provides a drive output which can be connected through a current limiting resistor to the gate of a mosfet. the driver output is capable of delivering drive pulses with a rise time of 40 ns, and a fall time of 15 ns through its internal source and sink resistance of 12.3 ohms (typical), measured with a 1.0 nf capacitive load. startup sequence the ncp1230 has an internal high voltage startup circuit (pin 8) which is connected to the high voltage dc bus (refer to figure 36). when power is applied to the bus, the ncp1230 internal current source (typically 3.2 ma) is biased and charges up the external vcc capacitor on pin 6, refer to figure 38. when the voltage on pin 6 (vcc) reaches vccoff (12.6 v typically), the current source is turned off reducing the amount of power being dissipated in the chip. the ncp1230 then turns on the drive output to the external mosfet in an attempt to increase the output voltage and charge up the vcc capacitor through the v aux winding in the transformer. during the startup sequence, the controller pushes for the maximum peak current, which is reached after the 2.5 ms soft ? start period. as soon as the maximum peak set point is reached, the internal 1.0 v zener diode actively limits the current amplitude to 1.0 v/rsense and asserts an error flag indicating that a maximum current condition is being observed. in this mode, the controller must determine if it is a normal startup period (or transient load) or is the controller is facing a fault condition. to determine the difference between a normal startup sequence, and a fault condition, the error flag is asserted, and the 125 ms timer starts to count down. if the error flag drops prior to the 125 ms time ? out period, the controller resets the timer and determines that it was a normal startup sequence and enables the low impedance switch (sw1), enabling the pfc_vcc output. if at the end of the 125 ms period the error flag is still asserted, then the controller assumes that it is a fault condition and the pwm controller enters the skip mode and does not enable the pfc_vcc output. figure 38. ? + 8 6 4 3.2 ma or 0 cvcc aux hv 12.6 v/ 5.6 v on semiconductor recommends that the vcc capacitor be at least 47 f to be sure that the vcc supply voltage does not drop below vccmin (7.7 v typical) during standby power mode and unusual fault conditions. soft ? start the ncp1230 features an internal 2.5 ms soft ? start circuit. as soon as vcc reaches a nominal 12.6 v, the soft ? start circuit is activated. the soft ? start circuit output controls a reference on the minus ( ? ) input to an amplifier (refer to figure 39), the positive (+) input to the amplifier is the feedback input (divided by 3). the output of the amplifier drives a fet which clamps the feedback signal. as the soft ? start circuit output ramps up, it allow the feedback pin input to the pwm comparator to gradually increased from near zero up to the maximum clamping level of 1.0 v/rsense. this occurs over the entire 2.5 ms soft ? start period until the supply enters regulation. the soft ? start is also activated every time a restart is attempted. figure 40 shows a typical soft ? start up sequence.
ncp1230 http://onsemi.com 17 figure 39. + - - + vdd_fb vdd pwm error cs fb osc 2.5 msec ss timer soft ? start ramp (1v max) skip comparators 10v 25k 20k 55k 2 figure 40. soft ? start is activated during a startup sequence or an ocp condition current sense max i p 12.6 v v cc 0 v (fresh pon) or 6 v (ocp) 2.5 ms
ncp1230 http://onsemi.com 18 frequency jittering frequency jittering is a method used to soften the emi signature by spreading out the average switching energy around the controller operating switching frequency. the ncp1230 of fers a nominal 6.4% deviation of the nominal switching frequency. the sweep sawtooth is internally generated and modulates the clock up and down with a 5 ms period. figure 41 illustrates the ncp1230 behavior: figure 41. an internal ramp is used to introduce frequency jittering on the oscillator saw tooth internal ramp 62.4 khz 67.6 khz 65 khz 5 ms internal sawtooth thermal protection an internal thermal shutdown is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated (165 c typically) the controller turns off the pwm drive output. when this occurs, vcc will drop (the rate is dependent on the ncp1230 loading and the size of the vcc capacitor) because the controller is no longer delivering drive pulses to the auxiliary winding charging up the vcc capacitor. when vcc drops below 4.0 volts and the vccreset circuit is activated, the controller will restart. if the user is using a fixed bias supply (the bias supply is provided from a source other than from an auxiliary winding, refer to the typical application ) and vcc is not allow to drop below 4.0 volts under a thermal shutdown condition, the ncp1230 will not restart. this feature is provided to prevent catastrophic failure from accidentally overheating the device.
ncp1230 http://onsemi.com 19 package dimensions soic ? 7 d1 suffix case 751u ? 01 issue c seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? a ? ? b ? g m b m 0.25 (0.010) ? t ? b m 0.25 (0.010) t s a s m 7 pl
ncp1230 http://onsemi.com 20 package dimensions soic ? 8 d suffix case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1230 http://onsemi.com 21 package dimensions 7 ? lead pdip p suffix case 626b ? 01 issue a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension l to center of lead when formed parallel. 4. package contour optional (round or square corners). 5. dimensions a and b are datums. 14 5 8 f note 2 ? t ? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max millimeters a 9.40 10.16 b 6.10 6.60 c 3.94 4.45 d 0.38 0.51 f 1.02 1.78 g 2.54 bsc h 0.76 1.27 j 0.20 0.30 k 2.92 3.43 l 7.62 bsc m ??? 10 n 0.76 1.01 a b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1230/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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